The present invention relates to the field of computer systems. Specifically, the present invention relates to a method and apparatus for staggering execution of an instruction.
Multimedia applications such as 2D/3D graphics, image processing, video compression/decompression, voice recognition algorithms and audio manipulation, require performing the same operation on a large number of data items (referred to as xe2x80x9cdata parallelismxe2x80x9d) which may be represented in a small number of bits. For example, graphical and sound data are typically represented by 32-bits in floating point format and 8 or 16 bits in integer format. Floating point numbers are represented in a computer system in the form of a digit string including three components: a sign, an exponent (indicating the magnitude of the number) and a significand or mantissa (indicating the value of the fractional portion of the number). Each type of multimedia application implements one or more algorithms, where each algorithm may require a number of floating point or integer operations, such as ADD or MULTIPLY (hereafter MUL).
Single Instruction Multiple Data (SIMD) technology has enabled a significant improvement in multimedia application performance. SIMD technology provides for a single macro instruction who execution causes a processor to perform the same operation on multiple data items in parallel. This technology is especially suited to systems that provide packed data formats. A packed data format is one in which the bits in a register are logically divided into a number of fixed-sized data elements, each of which represents a separate value. For example, a 64-bit register may be broken into four 16-bit elements, each of which represents a separate 16-bit value. SIMD instructions then separately manipulate each element in these packed data types in parallel. For example, a SIMD packed ADD instruction adds together corresponding data elements from a first packed data operand and a second packed data operand, as illustrated in FIG. 1. More specifically, the corresponding data elements for X and Y are added to result in Z, i.e. X0+Y0=Z0, X1+Y1=Z1, X2+Y2=Z2 and X3+Y3=Z3.
FIGS. 2A-2B illustrate a current processor implementation of an arithmetic logic unit (ALU) that can be used to execute SIMD instructions. The ALU of FIG. 2A includes the circuitry necessary to perform operations on the full width of the operands (i.e. all of the data elements) FIG. 2A also shows that the ALU contains two different type of execution units for respectively performing different types of operations (e.g. certain ALUs use separate units for performing ADD and MUL operations). This example assumes that the processor execution engine is capable of processing one instruction per clock cycle. The four ADD execution units and four MUL execution units are respectively capable of operating as four separate ADD execution units and four separate MUL execution units. Alternatively, the ALU may contain multiple Floating Point Multiply Accumulate (FMAC) units, each capable of performing more than a single type of operation. The following examples assume the use of ADD and MUL execution units, but other execution units such as FMAC may also be used.
Thus, as illustrated in FIG. 2B, if at time T, an xe2x80x9cADD X, Yxe2x80x9d instruction is issued via issue port 105, each of the four ADD execution units performs an ADD on the separate packed data elements. The four MUL units remain idle during time T. At time T+1, assuming an xe2x80x9cADD A, Bxe2x80x9d instruction is issued, each of the four ADD execution units once again performs an ADD on the separate packed data elements, while the four MUL units once again remain idle. At time T+2, if a xe2x80x9cMUL X, Yxe2x80x9d instruction is issued, then each of the four MUL units separately performs a MUL on one of the four packed data elements, while the four ADD execution units remain idle. Finally, at time T+3, if an xe2x80x9cADD S, Txe2x80x9d instruction is issued, then each of the four ADD execution units perform ADDs while the four MUL units remain idle.
The implementation described above can require a significant amount of duplicated hardware components and is inefficient in utilizing the hardware components (namely the ADD and MUL execution units). At any given time, one execution unit remains idle while the second execution unit is active. Once again, this example assumes that the processor execution engine is capable of processing one instruction per clock cycle.
The present invention discloses a method and apparatus for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description.